View AD9763_1093916.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9763 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 10-bit, 125 msps dual txdac+ d/a converter functional block diagram ? latch ? dac refio fsadj1 fsadj2 gainctrl reference bias generator i outa1 i outb1 sleep i outa2 i outb2 digital interface AD9763 port1 port2 wrt1 wrt2 dvdd dcom avdd acom clk1 clk2 mode ? dac ? latch features 10-bit dual transmit dac 125 msps update rate excellent sfdr and imd: 78 dbc excellent gain and offset matching: 0.1% fully independent or single resistor gain control dual port or interleaved data on-chip 1.2 v reference single 5 v or 3 v supply operation power dissipation: 380 mw @ 5 v power-down mode: 50 mw @ 5 v 48-lead lqfp applications communications base stations digital synthesis quadrature modulation product description the AD9763 is a dual port, high speed, two-channel, 10-bit cmos dac. it integrates two high quality 10-bit txdac+ cores, a voltage reference and digital interface circuitry into a small 48-lead lqfp package. the AD9763 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the AD9763 has been optimized for processing i and q data in communications applications. the digital interface consists of two double-buffered latches as well as control logic. separate write inputs allow data to be written to the two dac ports independent of one another. separate clocks control the update rate of the dacs. a mode control pin allows the AD9763 to interface to two sep arate data ports, or to a single interleaved high speed data port. in inter- leaving mode the input data stream is demuxed into its original i and q data and then latched. the i and q data is then con- verted by the two dacs and updated at half the input data rate. the gainctrl pin allows two modes for setting the full-scale current (i outfs ) of the two dacs. i outfs for each dac can be set independently using two external resistors, or i outfs for both dacs can be set by using a single external resistor. ** the dacs utilize a segmented current source architecture com- bined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. each dac provides differential current output thus supporting single-ended or differential applications. both dacs can be simultaneously updated and provide a nominal full-scale current of 20 ma. the full-scale currents between each dac are matched to within 0.1%. the AD9763 is manufactured on an advanced low cost cmos process. it operates from a single supply of 3.0 v to 5.0 v and consumes 380 mw of power. product highlights 1. the AD9763 is a member of a pin-compatible family of dual txdacs providing 8-, 10-, 12- and 14-bit resolution. 2. dual 10-bit, 125 msps dacs: a pair of high performance dacs optimized for low distortion performance provide for flexible transmission of i and q information. 3. matching: gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. low power: complete cmos dual dac function operates on 380 mw from a 3.0 v to 5.0 v single supply. the dac full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference: the AD9763 includes a 1.20 v temperature-compensated bandgap voltage reference. 6. dual 10-bit inputs: the AD9763 features a flexible dual- port interface allowing dual or interleaved input data. txdac+ is a registered trademark of analog devices, inc. * * patent pending. ** please see gainctrl mode section, for important date code information on this feature.
rev. b ? AD9763?pecifications dc specifications (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted.) parameter min typ max units resolution 10 bits dc accuracy 1 integral linearity error (inl) ? 0.1 +1 lsb differential linearity error (dnl) ?.5 0.07 +0.5 lsb analog output offset error ?.02 +0.02 % of fsr gain error (without internal reference) ? 0.25 +2 % of fsr gain error (with internal reference) ? 1 +5 % of fsr gain match ?.6 0.1 +1.6 % of fsr ?.14 +0.14 db full-scale output current 2 2.0 20.0 ma output compliance range ?.0 +1.25 v output resistance 100 k ? output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m ? small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 3 5 5.5 v dvdd 2.7 5 5.5 v analog supply current (i avdd )7175ma digital supply current (i dvdd ) 4 57 ma digital supply current (i dvdd ) 5 15 ma supply current sleep mode (i avdd ) 8 12.0 ma power dissipation 4 (5 v, i outfs = 20 ma) 380 410 mw power dissipation 5 (5 v, i outfs = 20 ma) 420 450 mw power dissipation 6 (5 v, i outfs = 20 ma) 450 mw power supply rejection ratio 7 ?vdd ?.4 +0.4 % of fsr/v power supply rejection ratio 7 ?vdd ?.025 +0.025 % of fsr/v operating range ?0 +85 c notes 1 measured at i outa , driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 times the i ref current. 3 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 4 measured at f clock = 25 msps and f out = 1.0 mhz. 5 measured at f clock = 100 msps and f out = 1 mhz. 6 measured as unbuffered voltage output with i outfs = 20 ma and 50 ? r load at i outa and i outb , f clock = 100 msps and f out = 40 mhz. 7 10% power supply variation. specifications subject to change without notice.
rev. b 3 AD9763 dynamic specifications (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, differential tr ansformer coupled output, 50 doubly terminated, unless otherwise noted) parameter min typ max units dynamic performance maximum output update rate (f clock ) 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (90% to 10%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ hz output noise (i outfs = 2 ma) 30 pa/ hz ac linearity spurious-free dynamic range to nyquist f clock = 100 msps; f out = 1.00 mhz 0 dbfs output 69 78 dbc ? dbfs output 74 dbc ?2 dbfs output 69 dbc ?8 dbfs output 61 dbc f clock = 65 msps; f out = 1.00 mhz 79 dbc f clock = 65 msps; f out = 2.51 mhz 78 dbc f clock = 65 msps; f out = 5.02 mhz 75 dbc f clock = 65 msps; f out = 14.02 mhz 66 dbc f clock = 65 msps; f out = 25 mhz 55 dbc f clock = 125 msps; f out = 25 mhz 67 dbc f clock = 125 msps; f out = 40 mhz 60 dbc spurious-free dynamic range within a window f clock = 100 msps; f out = 1.00 mhz; 2 mhz span 78 85 dbc f clock = 50 msps; f out = 5.02 mhz; 10 mhz span 80 dbc f clock = 65 msps; f out = 5.03 mhz; 10 mhz span 82 dbc f clock = 125 msps; f out = 5.04 mhz; 10 mhz span 82 dbc total harmonic distortion f clock = 100 msps; f out = 1.00 mhz ?7 ?9 dbc f clock = 50 msps; f out = 2.00 mhz ?7 dbc f clock = 125 msps; f out = 4.00 mhz ?4 dbc f clock = 125 msps; f out = 10.00 mhz ?2 dbc multitone power ratio (eight tones at 110 khz spacing) f clock = 65 msps; f out = 2.00 mhz to 2.99 mhz 0 dbfs output 76 dbc ? dbfs output 74 dbc ?2 dbfs output 71 dbc ?8 dbfs output 67 dbc channel isolation f clock = 125 msps; f out = 10 mhz 85 dbc f clock = 125 msps; f out = 40 mhz 77 dbc notes 1 measured single-ended into 50 ? load. specifications subject to change without notice.
rev. b ? AD9763?pecifications digital specifications parameter min typ max units digital inputs logic ??voltage @ dvdd = +5 v 3.5 5 v logic ??@ dvdd = 3 2.1 3 v logic ??voltage @ dvdd = +5 v 0 1.3 v logic ??@ dvdd = 3 0 0.9 v logic ??current ?0 +10 a logic ??current ?0 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw, t cpw ) 3.5 ns specifications subject to change without notice. absolute maximum ratings * with parameter respect to min max units avdd acom ?.3 +6.5 v dvdd dcom ?.3 +6.5 v acom dcom ?.3 +0.3 v avdd dvdd ?.5 +6.5 v mode, clk1, clk2, wrt1, wrt2 dcom ?.3 dvdd + 0.3 v digital inputs dcom ?.3 dvdd + 0.3 v i outa1 /i outa2 , i outb1 /i outb2 acom ?.0 avdd + 0.3 v refio, fsadj1, fsadj2 acom ?.3 avdd + 0.3 v gainctrl, sleep acom ?.3 avdd + 0.3 v junction temperature +150 c storage temperature ?5 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating o nly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. data in (wrt2) (wrt1 / iqwrt) (clk2) (clk1/ iqclk) iouta or ioutb t lpw t pd t s t h t cpw figure 1. timing diagram for dual and interleaved modes see dynamic and digital sections for timing specifications. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted.) ordering guide temperature package package model range description option * AD9763ast ?0 c to +85 c 48-lead lqfp st-48 AD9763-eb evaluation board * st = thin plastic quad flatpack. thermal characteristics thermal resistance 48-lead lqfp ja = 91 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9763 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. b AD9763 5 pin function descriptions pin no. name description 1?0 port1 data bits db9?1 to db0?1. 11?4, 33?6 nc no connection. 15, 21 dcom1, dcom2 digital common. 16, 22 dvdd1, dvdd2 digital supply voltage. 17 wrt1/iqwrt input write signal for port 1 (iqwrt in interleaving mode). 18 clk1/iqclk clock input for dac1 (iqclk in interleaving mode). 19 clk2/iqreset clock input for dac2 (iqreset in interleaving mode). 20 wrt2/iqsel input write signal for port 2 (iqsel in interleaving mode). 23?2 port2 data bits db9?2 to db0?2. 37 sleep power-down control input. 38 acom analog common. 39, 40 i outa2 , i outb2 ?ort 2?differential dac current outputs. 41 fsadj2 full-scale current output adjust for dac2. 42 gainctrl gainctrl mode (0 = 2 resistor, 1 = 1 resistor.) 43 refio reference input/output. 44 fsadj1 full-scale current output adjust for dac1. 45, 46 i outb1 , i outa1 ?ort 1?differential dac current outputs. 47 avdd analog supply voltage. 48 mode mode select (1 = dual port, 0 = interleaved). pin configuration 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) 36 35 34 33 32 31 30 29 28 27 26 25 nc = no connect AD9763 nc nc nc nc db0-p2 db1-p2 db2-p2 db3-p2 db4-p2 db5-p2 db6-p2 db7-p2 db9-p1 (msb) db8-p1 db7-p1 db6-p1 db5-p1 db4-p1 db3-p1 db2-p1 db1-p1 db0-p1 nc nc mode avdd i outa1 i outb1 fsadj1 refio gainctrl fsadj2 i outb2 i outa2 acom sleep nc nc dcom1 dvdd1 wrt1/iqwrt clk1/iqclk clk2/iqreset wrt2/iqsel dcom2 dvdd2 db9-p2 (msb) db8-p2
rev. b AD9763 6 definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is reported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). i outa2 i outb2 5v 50 i outa1 i outb1 segmented switches for dac1 lsb switch segmented switches for dac2 lsb switch dac 2 latch dac 1 latch clk divider pmos current source array pmos current source array clk1/iqclk clk2/iqreset avdd fsadj1 refio fsadj2 1.2v ref channel 1 latch channel 2 latch mode dvdd multiplexing logic 5v wrt2/ iqsel wrt1/ iqwrt gainctrl 0.1 f r set 2 2k r set 1 2k 50 50 mini circuits t1-1t to hp3589a spectrum/ network analyzer dcom sleep acom db0 db9 db0 db9 digital data tektronix awg-2021 w/option 4 lecroy 9210 pulse generator *retimed clock output dvdd dcom AD9763 *awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock figure 2. basic ac characterization test setup for AD9763, testing port 1 in dual port mode, using independent gainctrl resistors on fsadj1 and fsadj2
rev. b AD9763 7 typical characterization curves (avdd = +5 v, dvdd = +3.3 v, i outfs = 20 ma, 50 doubly terminated load, differential output, t a = +25 c, sfdr up to nyquist, unless otherwise noted.) f out mhz sfdr dbc 90 80 50 100 110 60 70 5msps 25msps 65msps 125msps figure 3. sfdr vs. f out @ 0 dbfs f out mhz sfdr dbc 50 05 25 10 15 20 80 75 70 60 55 65 30 35 0dbfs 6dbfs 12dbfs figure 6. sfdr vs. f out @ 65 msps a out dbfs sfdr dbc 55 0 20 16 8 85 60 70 65 75 80 12 4 910khz/10msps 5.91mhz/65msps 2.27mhz/25msps 11.37mhz/125msps figure 9. single-tone sfdr vs. a out @ f out = f clock /11 f out mhz sfdr dbc 0.00 2.50 0.50 1.00 1.50 2.00 80 75 70 65 0dbfs 6dbfs 12dbfs figure 4. sfdr vs. f out @ 5 msps f out mhz sfdr dbc 50 010 50 20 30 40 80 75 70 60 55 65 60 70 0dbfs 6dbfs 12dbfs figure 7. sfdr vs. f out @ 125 msps a out dbfs sfdr dbc 60 0 20 16 4 80 65 70 55 75 85 12 8 5mhz/25msps 1mhz/5msps 2mhz/10msps 13mhz/65msps 25mhz/125msps figure 10. single-tone sfdr vs. a out @ f out = f clock /5 f out mhz sfdr dbc 0 2 12 4 6 8 10 80 75 70 60 65 0dbfs 6dbfs 12dbfs figure 5. sfdr vs. f out @ 25 msps f out mhz sfdr dbc 50 0 10 20 30 80 75 70 60 55 65 5152535 i outfs = 5ma i outfs = 10ma i outfs = 20ma figure 8. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs a out dbfs sfdr dbc 80 0 20 12 8 4 70 55 65 75 16 60 3.38/3.36mhz@25msps 0.965/1.035mhz@7msps 6.75/7.25mhz@65msps 16.9/18.1mhz@125msps figure 11. dual-tone sfdr vs. a out @ f out = f clock /7
rev. b AD9763 8 f clock msps sinad dbc 55 20 140 40 60 80 100 120 60 65 70 i outfs = 5ma i outfs = 10ma i outfs = 20ma figure 12. sinad vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs temperature c sfdr dbc 80 75 50 40 20 80 60 70 65 60 55 40 20 0 45 100 60 85 f out = 10mhz f out = 1mhz f out = 25mhz f out = 40mhz f out = 60mhz figure 15. sfdr vs. temperature @ 125 msps, 0 dbfs frequency mhz dbm 40 20 0 90 80 70 60 50 40 30 20 10 0 10 30 figure 18. dual-tone sfdr @ f clk = 125 msps figure 13. typical inl temperature c offset error % fs 0.05 0.05 40 200 20406080 0.03 0.00 0.03 gain error offset error 1.0 1.0 0.5 0.00 0.5 gain error % fs figure 16. reference voltage drift vs. temperature frequency mhz dbm 40 20 0 90 80 70 60 50 40 30 20 10 0 10 30 figure 19. four-tone sfdr @ f clk = 125 msps figure 14. typical dnl frequency mhz dbm 40 20 0 90 80 70 60 50 40 30 20 10 0 10 10 30 figure 17. single-tone sfdr @ f clk = 125 msps code inl lsbs 0.25 0.20 0.15 0.10 0.05 0 0.05 0.10 0.15 0.20 0 200 400 600 800 1000 0.25 code dnl lsbs 0.01 0 200 0.05 0 0.05 0.25 0.30 0.20 0.15 0.10 400 600 800 1000
rev. b AD9763 9 functional description figure 20 shows a simplified block diagram of the AD9763. the AD9763 consists of two dacs, each one with its own independent digital control logic and full-scale output current control. each dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsb is a binary weighted fraction of the middle bit current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances the dynamic performance for multitone or low amplitude signals and helps maintain the dac? high output impedance (i.e., >100 k ? ). all of these current sources are switched to one or the other of the two output nodes (i.e., i outa or i outb ) via pmos differential current switches. the switches are based on a new architecture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the AD9763 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 3 v to 5.5 v range. the digital section, which is capable of operating up to a 125 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v bandgap voltage reference and two reference control amplifiers. the full-scale output current of each dac is regulated by sepa- rate reference control amplifiers and can be set from 2 ma to 20 ma via an external resistor, r set , connected to the full scale adjust (fsadj) pin. the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 i ref . i outa2 i outb2 5v i outa1 i outb1 segmented switches for dac1 lsb switch segmented switches for dac2 lsb switch dac 2 latch dac 1 latch clk divider pmos current source array pmos current source array clk1/iqclk clk2/iqreset avdd fsadj1 refio fsadj2 1.2v ref channel 1 latch channel 2 latch mode dvdd multiplexing logic 5v wrt2/ iqsel wrt1/ iqwrt gainctrl 0.1 f r set 2 2k r set 1 2k dcom sleep acom db0 db9 db0 db9 digital data inputs AD9763 i ref 1 i ref 2 r l 2b 50 r l 2a 50 v out 2b v out 2a r l 1b 50 r l 1a 50 v out 1b v out 1a v diff = v out a v out b figure 20. simplified block diagram reference operation the AD9763 contains an internal 1.20 v bandgap reference. this can easily be overridden by an external reference with no effect on performance. refio serves as either an input or out- put , depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor. the internal reference voltage will be present at refio. if the voltage at refio is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in figure 21. +1.2v ref avdd gainctrl current source array refio fsadj 2k 0.1 f additional external load optional external reference buffer AD9763 reference section i ref acom figure 21. internal reference configuration an external reference can be applied to refio as shown in figure 22. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal refer- ence is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference. +1.2v ref avdd gainctrl current source array refio fsadj 2k AD9763 reference section i ref acom avdd external reference figure 22. external reference configuration
rev. b AD9763 10 gainctrl mode the AD9763 allows the gain of each channel to be independently set by connecting one r set resistor to fsadj1 and another r set resistor to fsadj2. to add flexibility and reduce system cost, a single r set resistor can be used to set the gain of both channels simultaneously. when gainctrl is low (i.e., connected to agnd), the inde- pendent channel gain control mode using two resistors is enabled. in this mode, individual r set resistors should be connected to fsadj1 and fsadj2. when gainctrl is high (i.e., connected to avdd), the master/slave channel gain control mode using one resistor is enabled. in this mode, a single r set resistor is connected to fsadj1 and the resistor on fsadj2 must be removed. note: only parts with date code of 9930 or later have the master/slave gainctrl function. for parts with a date code before 9930, pin 42 must be connected to agnd, and the part will operate in the two resistor, independent gain control mode. reference control amplifier both of the dacs in the AD9763 contain a control amplifier that is used to regulate the full-scale output current, i outfs . the control amplifier is configured as a v-i converter as shown in figure 21, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs as stated in equa- tion 3. the control amplifier allows a wide (10:1) adjustment span of i outfs from 2 ma to 20 ma by setting i ref between 62.5 a and 625 a. the wide adjustment range of i outfs provides several benefits. the first relates directly to the power dissi- pation of the AD9763, which is proportional to i outfs (refer to the power dissipation section). the second relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency, small signal multiplying applications. dac transfer function both dacs in the AD9763 provide complemen tary current outputs, i outa and i outb . i outa will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 1023) while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as: i outa = ( dac code /1024) i outfs (1) i outb = (1023 ? dac code )/1024) i outfs (2) where dac code = 0 to 1023 (i.e., decimal representation). as previously mentioned, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load di- rectly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 ? or 75 ? cable. the single-ended voltage output appearing at the i outa and i outb nodes is simply: v outa = i outa r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. v diff = ( i outa ?i outb ) r load (7) substituting the values of i outa , i outb and i ref ; v diff can be expressed as: v diff = {(2 dac code ?1023)/1024} (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the AD9763 differentially. first, the differential opera- tion will help cancel common-mode error sources associated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the AD9763 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. analog outputs the complementary current outputs in each dac, i outa and i outb , may be configured for single-ended or differential opera- tion. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resis- tor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , exist- ing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the AD9763 is optimum and specified using a differential transformer coupled output in which the voltage swing at i outa and i outb is limited to 0.5 v. if a single-ended unipolar output is desirable, i outa should be selected. the distortion and noise performance of the AD9763 can be enhanced when it is configured for differential operation. the common-mode error sources of both i outa and i outb can be significantly reduced by the common-mode rejection of a trans- former or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more signifi- cant as the frequency content of the reconstructed waveform increases. this is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feed- through and noise.
rev. b AD9763 11 performing a differential-to-single-ended conversion via a trans- former also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). since the output currents of i outa and i outb are complemen- tary, they become additive when processed differentially. a properly selected transformer will allow the AD9763 to provide the required power and voltage levels to different loads. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos switches associ- ated with the current sources and is typically 100 k ? in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining i outa and/or i outb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note the inl/dnl specifications for the AD9763 are measured with i outa maintained at a virtual ground via an op amp. i outa and i outb also have a negative and positive voltage com- pliance range that must be adhered to in order to achieve opti- mum performance. the negative output compliance range of ?.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9763. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. the optimum distortion performance for a single-ended or differential output is achieved when the maxi- mum full-scale signal at i outa and i outb does not exceed 0.5 v. applications requiring the AD9763? output (i.e., v outa and/or v outb ) to extend its output compliance range should size r load accordingly. operation beyond this compliance range will adversely affect the AD9763? linearity performance and subsequently degrade its distortion performance. digital inputs the AD9763? digital inputs consist of two independent chan- nels. for the dual port mode, each dac has its own dedicated 10-bit data port, wrt line and clk line. in the interleaved timing mode, the function of the digital control pins changes as described in the interleaved mode timing section. the 10-bit parallel data inputs follow straight binary coding where db9 is the most significant bit (msb) and db0 is the least significant bit (lsb). i outa produces a full-scale output current when all data bits are at logic 1. i outb produces a complementary out- put with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. the dac outputs are updated following either the rising edge, or every other rising edge of the clock, depending on whether dual or interleaved mode is being used. the dac outputs are designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transi- tion edges may affect digital feedthrough and distortion perfor- mance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. dac timing the AD9763 can operate in two timing modes, dual and inter- leaved, which are described below. the block diagram in figure 25 represents the latch architecture in the interleaved timing mode. dual port mode timing for the following section, refer to figure 2. when the mode pin is at logic 1, the AD9763 operates in dual port mode. the AD9763 functions as two distinct dacs. each dac has its own completely independent digital input and control lines. the AD9763 features a double buffered data path. data enters the device through the channel input latches. this data is then transferred to the dac latch in each signal path. once the data is loaded into the dac latch, the analog output will settle to its new value. for general consideration, the wrt lines control the channel input latches and the clk lines control the dac latches. both sets of latches are updated on the rising edge of their respective control signals. the rising edge of clk should occur before or simultaneously with the rising edge of wrt. should the rising edge of clk occur after the rising edge of wrt, a 2 ns minimum delay should be maintained from the rising edge of wrt to the rising edge of clk. timing speci?ations for dual port mode are given in figures 23 and 24. wrt1/wrt2 clk1/clk2 data in iouta or ioutb t lpw t pd t s t h t cpw figure 23. dual mode timing d1 d2 d3 d4 d5 datain wrt1/wrt2 clk1/clk2 xx d1 d2 d3 d4 iouta or ioutb figure 24. dual mode timing
rev. b AD9763 12 interleaved mode timing for the following section, refer to figure 25. when the mode pin is at logic 0, the AD9763 operates in interleaved mode. wrt1 now functions as iqwrt and clk1 functions as iqclk. wrt2 functions as iqsel and clk2 functions as iqreset. data enters the device on the rising edge of iqwrt. the logic level of iqsel will steer the data to either channel latch 1 (iqsel = 1) or to channel latch 2 (iqsel = 0). when iqreset is high, iqclk is disabled. when iqreset goes low, the following rising edge on iqclk will update both dac latches with the data present at their inputs. in the inter- leaved mode, iqclk is divided by 2 internally. following this first rising edge, the dac latches will only be updated on every other rising edge of iqclk. in this way, iqreset can be used to synchronize the routing of the data to the dacs. as with the dual port mode, iqclk should occur before or simultaneously with iqwrt. iqsel iqwrt dac1 latch dac1 interleaved data in, port 1 deinterleaved data out iqclk iqreset dac2 latch dac2 2 port 1 input latch port 2 input latch figure 25. latch structure interleaved mode timing specifications for interleaved mode are given in figures 26 and 27. the digital inputs are cmos-compatible with logic thresholds, v threshold , set to approximately half the digital positive supply (dvdd) or v threshold = dvdd/2 ( 20 % ) data in iqwrt iqclk iouta or ioutb t lpw t pd t s t h t cpw figure 26. interleaved mode timing d1 d2 d3 d4 d5 interleaved data xx xx d1 d2 d3 d4 xx (wrt2) iqsel (wrt1) iqwrt (clk1) iqclk (external) (clk2) iqreset dac output port 1 dac output port 2 iqclk 2 (external) figure 27. interleaved mode timing the internal digital circuitry of the AD9763 is capable of oper- ating over a digital supply range of 3 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh (max). a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. fig- ure 28 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar with the excep- tion that it contains an active pull-down circuit, thus en suring that the AD9763 remains enabled if this input is left discon- nected. since the AD9763 is capable of being clocked up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. operating the AD9763 with reduced logic swings and a corresponding digital supply (dvdd) will result in the lowest data feedthrough and on-chip digital noise. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9763 as well as its required min/max input logic level thresholds. digital signal paths should be kept short and run lengths m atched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 ? to 100 ? ) between the AD9763 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. for longer board traces and high data up- date rates, stripline techniques with proper impedance and termination resistors should be considered to maintain ?lean digital inputs. the external clock driver circuitry should provide the AD9763 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application.
rev. b AD9763 13 note that the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., dvdd/2) and meets the min/max logic threshold. this will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effec- tive clock duty cycle and, subsequently, cut into the required data setup and hold times. dvdd digital input figure 28. equivalent digital input input clock and data timing relationship snr in a dac is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. the AD9763 is rising edge triggered, and so exhibits snr sensitivity when the data transition is close to this edge. in general, the goal when applying the AD9763 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 29 shows the relationship of snr to clock placement with different sample rates. note that at the lower sample rates, much more tolerance is allowed in clock placement, while much more care must be taken at higher rates. time of data change relative to rising clock edge ns snr dbc 0 4 2 0 23 3 1 4 1 10 20 30 40 50 60 70 figure 29. snr vs. clock placement @ f out = 20 mhz and f clk = 125 msps sleep mode operation the AD9763 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 3.0 v to 5.5 v and temperature range. this mode can be activated by applying a logic level ??to the sleep pin. the sleep pin logic thresh- old is equal to 0.5 avdd. this digital input also contains an active pull-down circuit that ensures the AD9763 remains enabled if this input is left disconnected. the AD9763 takes less than 50 ns to power down and approximately 5 s to power back up. power dissipation the power dissipation, p d , of the AD9763 is dependent on several factors that include: (1) the power supply voltages (avdd and dvdd), (2) the full-scale current output i outfs , (3) the update rate f clock , (4) and the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs as shown in figure 30 and is insensitive to f clock . i outfs 0510 10 i avdd 20 30 40 50 60 70 80 15 20 25 figure 30. i avdd vs. i outfs conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 31 and 32 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. ratio f out /f clk 0 0.10 0 i dvdd ma 5 10 15 20 25 30 35 0.20 0.30 0.40 0.50 125msps 100msps 65msps 25msps 5msps figure 31. i dvdd vs. ratio @ dvdd = 5 v
rev. b AD9763 14 ratio f out /f clk 0 0.10 0 i dvdd ma 2 4 6 8 10 12 14 0.20 0.30 0.40 0.50 16 18 125msps 100msps 65msps 25msps 5msps figure 32. i dvdd vs. ratio @ dvdd = 3 v applying the AD9763 output configurations the following sections illustrate some typical output configura- tions for the AD9763. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level-shifting, within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropriately- sized load resistor, r load , referred to acom. this configuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus convert- ing i outa or i outb into a negative unipolar voltage. this con- figuration provides the best dc linearity since i outa or i outb is maintained at a virtual ground. note that i outa provides slightly better performance than i outb . differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 33. a differentially coupled transformer output provides the opti- mum distortion performance for output signals whose spectral content lies within the transformer? passband. an rf trans- former such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-order har- monics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load AD9763 mini-circuits t1-1t optional r diff i outa i outb figure 33. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appear- ing at i outa and i outb (i.e., v outa and v outb ) swing symmetri- cally around acom and should be maintained with the specified output compliance range of the AD9763. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive re con- struction filter or cable. r diff is determined by the transformer? impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion as shown in figure 34. the AD9763 is con- figured with two equal load resistors, r load , of 25 ? . the different ial voltage developed across i outa and i outb is con- verted to a single-ended signal via the differential op amp con- figuration. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion perfor- mance by preventing the dacs high slewing output from over- loading the op amp? input. the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential perfor- mance of the AD9763, while meeting other system level objectives (i.e., cost, power), should be selected. the op amp? differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. AD9763 i outa i outb 500 225 225 500 25 25 ad8047 c opt figure 34. dc differential coupling using an op amp
rev. b AD9763 15 the differential circuit shown in figure 35 provides the neces- sary level-shifting required in a single supply system. in this case avdd, which is the positive analog supply for both the AD9763 and the op amp, is also used to level-shift the differ- ential output of the AD9763 to midsupply (i.e., avdd/2). the ad8055 is a suitable op amp for this application. AD9763 i outa i outb c opt 500 225 225 500 25 25 ad8055 1k avdd figure 35. single supply dc differential coupled circuit single-ended unbuffered voltage output figure 36 shows the AD9763 configured to provide a unipolar output range of approximately 0 v to +0.5 v for a doubly ter- minated 50 ? cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 ? . in this case, r load represents the equivalent load resistance seen by i outa or i outb . the unused output (i outa or i outb ) can be connected to acom directly or via a matching r load . differ- ent values of i outfs and r load can be selected as long as the positive compli ance range is adhered to. one additional con- sideration in this mode is the integral nonlinearity (inl) as discussed in the a nalog output section of this data sheet. for opti mum inl performance, the single-ended, buffered voltage output configuration is suggested. AD9763 i outa i outb 50 25 50 v outa = 0 to +0.5v i outfs = 20ma figure 36. 0 v to 0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 37 shows a buffered single-ended output configura- tion in which the op amp u1 performs an i-v conversion on the AD9763 output current. u1 maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output imped- ance e ffect on the dac? inl performance as discussed in the analog output section. although this single-ended configu- ration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1? slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is sim- ply the product of r fb and i outfs . the full-scale output should be set within u1? voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion perfor- mance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. AD9763 i outa i outb c opt 200 u1 v out = i outfs r fb i outfs = 10ma r fb 200 figure 37. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these application cir- cuits, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf tech- niques must be used for device selection, placement and rout- ing, as well as power supply bypassing and grounding to ensure optimum performance. figures 44 to 51 illustrate the recom- mended printed circuit board ground, power and signal plane layouts which are implemented on the AD9763 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio. for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dac? full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is gener- ated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr vs. frequency of the AD9763 avdd supply over this frequency range is shown in figure 38. frequency mhz psrr db 90 70 0.20 85 80 75 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 figure 38. power supply rejection ratio of AD9763 note that the units in figure 38 are given in units of (amps out/ volts in). noise on the analog power supply has the effect of modulating the internal current sources, and therefore the out- put current. the voltage noise on avdd, therefore, will be added in a nonlinear manner to the desired i out . psrr is very code-dependent thus producing mixing effects which can modu- late low frequency power supply noise to higher frequencies.
rev. b AD9763 16 worst case psrr for either one of the differential dac outputs will occur when the full-scale current is directed towards that output. as a result, the psrr measurement in figure 38 repre- sents a worst case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simplic- ity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dac? full-scale current, i outfs , one must determine the psrr in db using figure 38 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 38 by the scaling factor 20 log (r load ). for instance, if r load is 50 ? , the psrr is reduced by 34 db (i.e., psrr of the dac at 250 khz, which is 85 db in figure 38, becomes 51 db v out /v in ). proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the AD9763 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be de- coupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single +5 v or +3 v supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 39. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low esr type electrolytic and tantalum capacitors. 100 f 10 22 f 0.1 f ttl/cmos logic circuits +5v power supply ferrite beads avdd acom electrolytic tantalum ceramic figure 39. differential lc filter for single +5 v and +3 v applications applications using the AD9763 for quadrature amplitude modulation qam is one of the most widely used digital modulation schemes in digital communications systems. this modulation technique can be found in fdm as well as spread spectrum (i.e., cdma) based systems. a qam signal is a carrier frequency that is modu- lated in both amplitude (i.e., am modulation) and phase (i.e., pm modulation). it can be generated by independently modu- lating two carriers of identical frequency but with a 90 phase difference. this results in an in-phase (i) carrier component and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specified carrier frequency. a common and traditional implementation of a qam modula- tor is shown in figure 40. the modulation is performed in the analog domain in which two dacs are used to generate the baseband i and q components. each component is then typi- cally applied to a nyquist filter before being applied to a quadrature mixer. the matching nyquist filters shape and limit each component? spectral envelope while minimizing intersym- bol interference. the dac is typically updated at the qam symbol rate or possibly a multiple of it if an interpolating filter precedes the dac. the use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. a quadrature mixer modulates the i and q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the qam signal. dac carrier frequency 10 10 to mixer nyquist filters quadrature modulator dac dsp or asic 0 90 figure 40. typical analog qam architecture in this implementation, it is much more difficult to maintain proper gain and phase matching between the i and q channels. the circuit implementation shown in figure 41 helps improve upon the matching between the i and q channels, as well as showing a path for upconversion using the ad8346 quadrature modulator. the AD9763 provides both i and q dacs as well as a common reference that will improve the gain matching and stability. r cal can be used to compensate for any mismatch in gain between the two channels. the mismatch may be attrib- uted to the mismatch between r set1 and r set2 , effective load resistance of each channel, and/or the voltage offset of the con- trol amplifier in each dac. the differential voltage outputs of both dacs in the AD9763 are fed into the respective differen- tial inputs of the ad8346 via matching networks.
rev. b AD9763 17 i and q digital data can be fed into the AD9763 in two different ways. in dual port mode, the digital i information drives one input port, while the digital q information drives the other input port. if no interpolation filter precedes the dac, the symbol rate will be the rate at which the system clock drives the clk and wrt pins on the AD9763. in interleaved mode, the digital input stream at port 1 contains the i and the q information in alternating digital words. using iqsel and iqreset, the AD9763 can be synchronized to the i and q data stream. the internal timing of the AD9763 routes the selected i and q data to the correct dac output. in interleaved mode, if no interpola- tion filter precedes the AD9763, the symbol rate will be half that of the system clock driving the digital data stream and the iqwrt and iqclk pins on the AD9763. cdma carrier division multiple access, or cdma, is an air transmit/ receive scheme where the signal in the transmit path is modu- lated with a pseudorandom digital code (sometimes referred to as the spreading code). the effect of this is to spread the trans- mitted signal across a wide spectrum. similar to a dmt wave- form, a cdma waveform containing multiple subscribers can be characterized as having a high peak to average ratio (i.e., crest factor), thus demanding highly linear components in the transmit signal path. the bandwidth of the spectrum is defined by the cdma standard being used, and in operation is imple- mented by using a spreading code with particular characteristics. distortion in the transmit path can lead to power being trans- mitted out of the defined band. the ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (acp). this is a regulatory issue due to the possibility of interference with other signals being transmitted by air. regula- tory bodies define a spectral mask outside of the transmit band, and the acp must fall under this mask. if distortion in the transmit path causes the acp to be above the spectral mask, then filtering, or different component selection, is needed to meet the mask requirements. figure 42 shows the AD9763, when used with the ad8346, reconstructing a wideband cdma signal at 1.8 ghz. the baseband signal is being sampled at 65 msps and has a chip rate of 8m chips. == 80 120 70 90 110 50 60 100 40 center 2.4ghz 3mhz span 30mhz 130 30 db c11 cu1 cu1 c0 c0 c11 frequency figure 42. cdma signal, 8 m chips sampled at 65 msps, recreated at 2.4 ghz, adjacent channel power > 60 dbm ( q dac ) iouta ioutb qouta qoutb dcom fsadj2 refio sleep r set2 3.74k 0.1 f clk2 q data input i data input dvdd avdd 500 200 c filter 500 2.5k 2.5k 2.5k 200 0.1 f 5v vpbf bbip bbin bbqp bbqn ad8346 loipp loipn vout note: 500 resistor network - ohmtek orn series 2.5k resistor network gainctrl clk1 fsadj1 r set1 3.83k r cal 200 500 + input latches phase splitter 200 500 200 c filter 500 200 dac latches dac dac latches dac ( i dac ) input latches wrt1 wrt2 acom AD9763 u1 u2 i outfs 11ma figure 41. baseband qam implementation using an AD9763 and ad8346
rev. b AD9763 18 ( q dac ) iouta qouta qoutb dcom fsadj2 refio sleep r set2 1.9k 0.1 f clk2 q data input i data input dvdd avdd 500 100 500 500 iipp iipn iiqp iiqn ad6122 clk1 fsadj1 r set1 2k r cal 220 500 input latches 100 500 100 500 100 dac latches dac dac latches dac ( i dac ) input latches wrt1 wrt2 acom AD9763 u1 u2 loipp loipn 2 phase splitter refin vgain gain control txopp txopn gain control scale factor temperature compensation modopn modopp v cc v cc 3v 500 500 gainctrl ioutb figure 43. cdma transmit application using AD9763 and ad6122 figure 43 shows an example of the AD9763 used in a w-cdma transmitter application using the ad6122 cdma 3 v if sub- system. the ad6122 has functions, such as external gain con- trol and low distortion characteristics, needed for the superior adjacent channel power (acp) requirements of w-cdma. evaluation board general description the AD9763-eb is an evaluation board for the AD9763 10-bit dual d/a converter. careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9763 in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the AD9763 in various configurations. possible output configurations include transformer coupled, resistor terminated, and single and differ- ential outputs. the digital inputs can be used in dual port or interleaved mode, and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. when operating the AD9763, best performance is obtained when running the d igital supply (dvdd) at +3 v and the analog supply (avdd) at +5 v.
rev. b AD9763 19 14 12 11 9 7 10 13 dgnd;8 dvdd;16 tssop112 j clk q q pre clr u2 k wht tp29 wht tp30 wht tp31 wht tp32 dgnd;3,4,5 dgnd;3,4,5 dgnd;3,4,5 dgnd;3,4,5 s1 s2 s3 s4 wrt1in iqwrt clk1in iqclk clk2in reset wrt2in iqsel 1 2 r1 50 1 2 r2 50 1 2 r3 50 1 2 r4 50 1 2 3 jp5 jp16 1 2 3 a b jp4 1 2 3 a b jp3 2 3 5 6 4 1 dgnd;8 dvdd;16 tssop112 1 2 3 a b jp7 jp2 jp1 dvdd 1 2 3 a b jp6 dvdd /2 clock divider wrt1 clk1 clk2 wrt2 wht tp33 sleep 1 2 r13 50 sleep j clk q q pre clr u1 k dvdd 15 ic ic ab ic 1 2 3 a b jp9 dclkin1 dclkin2 red tp10 b1 ban-jack dvddin l1 bead 1 2 c9 10 f 25v blk tp37 blk tp38 tp43 blk blk tp39 dgnd dvdd b2 ban-jack red tp11 b3 ban-jack avddin l2 bead 1 2 c10 10 f 25v blk tp40 blk tp41 tp44 blk blk tp42 agnd avdd b4 ban-jack 1 2 c7 0.1 f 1 2 c8 0.01 f dvdd power decoupling and input clocks r1 22 inp1 2 1 rcom r2 22 inp2 3 r3 22 inp3 4 r4 22 inp4 5 r5 22 inp5 6 r6 22 inp6 7 r7 22 inp7 8 r8 22 inp8 9 r9 22 10 rp16 r1 22 inp9 2 1 rcom r2 22 inp10 3 r3 22 inp11 4 r4 22 inp12 5 r5 22 inp13 6 r6 22 inp14 7 r7 22 8 r8 22 inck1 9 r9 22 10 rp9 r1 22 inp23 2 1 rcom r2 22 inp24 3 r3 22 inp25 4 r4 22 inp26 5 r5 22 inp27 6 r6 22 inp28 7 r7 22 inp29 8 r8 22 inp30 9 r9 22 10 rp10 r1 22 inp31 2 1 rcom r2 22 inp32 3 r3 22 inp33 4 r4 22 inp34 5 r5 22 inp35 6 r6 22 inp36 7 r7 22 8 r8 22 inck2 9 r9 22 10 rp15 figure 44. power decoupling and clocks on AD9763 evaluation board
rev. b AD9763 20 rp11 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 116 rp5, 10 314 rp5, 10 512 rp5, 10 710 rp5, 10 116 rp6, 10 314 rp6, 10 512 rp6, 10 215 13 11 9 15 13 11 dvdd rp3 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp5, 10 4 rp5, 10 6 rp5, 10 8 rp5, 10 2 rp6, 10 4 rp6, 10 6 rp6, 10 89 rp6, 10 dutp1 dutp2 dutp3 dutp4 dutp5 dutp6 dutp7 dutp8 dutp9 dutp10 dutp11 dutp12 dutp13 dutp14 dclkin1 dvdd rp1 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp13 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 2 p1 p1 1 4 p1 p1 3 6 p1 p1 5 8 p1 p1 7 10 p1 p1 9 12 p1 p1 11 14 p1 p1 13 16 p1 p1 15 18 p1 p1 17 20 p1 p1 19 22 p1 p1 21 24 p1 p1 23 26 p1 p1 25 28 p1 p1 27 30 p1 p1 29 32 p1 p1 31 34 p1 p1 33 36 p1 p1 35 38 p1 p1 37 40 p1 p1 39 116 rp7, 10 314 rp7, 10 512 rp7, 10 710 rp7, 10 116 rp8, 10 314 rp8, 10 512 rp8, 10 215 13 11 9 15 13 11 rp7, 10 4 rp7, 10 6 rp7, 10 8 rp7, 10 2 rp8, 10 4 rp8, 10 6 rp8, 10 89 rp8, 10 dutp23 dutp24 dutp25 dutp26 dutp27 dutp28 dutp29 dutp30 dutp31 dutp32 dutp33 dutp34 dutp35 dutp36 dclkin2 710 rp5, 10 710 rp8, 10 spares 2 p2 p2 1 4 p2 p2 3 6 p2 p2 5 8 p2 p2 7 10 p2 p2 9 12 p2 p2 11 14 p2 p2 13 16 p2 p2 15 18 p2 p2 17 20 p2 p2 19 22 p2 p2 21 24 p2 p2 23 26 p2 p2 25 28 p2 p2 27 30 p2 p2 29 32 p2 p2 31 34 p2 p2 33 36 p2 p2 35 38 p2 p2 37 40 p2 p2 39 rp12 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 dvdd rp4 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 dvdd rp2 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 22 rp14 10 9 8 7 6 5 4 3 2 1 r1 r9 rcom 33 inp1 inp2 inp3 inp4 inp5 inp6 inp7 inp8 inp9 inp10 inp11 inp12 inp13 inp14 inck1 inck2 inp23 inp24 inp25 inp26 inp27 inp28 inp29 inp30 inp31 inp32 inp33 inp34 inp35 inp36 digital input signal conditioning figure 45. digital input signal conditioning
rev. b AD9763 21 wht tp46 12 r10 1.92k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 db13p1msb db12p1 db11p1 db10p1 db9p1 db8p1 db7p1 db6p1 db5p1 db4p1 db3p1 db2p1 db1p1 db0p1 dcom1 dvdd1 wrt1 clk1 clk2 wrt2 dcom2 dvdd2 db13p2msb db12p2 mode avdd ia1 ib1 fsadj1 refio gainctrl fsadj2 ib2 ia2 acom sleep db0p2 db1p2 db2p2 db3p2 db4p2 db5p2 db6p2 db7p2 db8p2 db9p2 db10p2 db11p2 u2 1 2 c1 val 1 2 c2 0.01 f 1 2 c3 0.1 f dvdd 1 2 3 a b jp8 dvdd 1 2 c11 1 f 1 2 c12 0.01 f 1 2 c13 0.1 f avdd sleep dutp36 dutp35 dutp34 dutp33 dutp32 dutp31 dutp30 dutp29 dutp28 dutp27 dutp26 dutp25 1 2 c15 10pf 1 2 r7 50 1 2 c6 10pf 1 2 r8 50 wrt1 clk1 clk2 wrt2 dutp23 dutp24 dutp1 dutp2 dutp3 dutp4 dutp5 dutp6 dutp7 dutp8 dutp9 dutp10 dutp11 dutp12 dutp13 dutp14 1 2 c4 10pf 1 2 r5 50 1 2 c5 10pf 1 2 r6 50 tp34 wht r11 val 1:1 3 2 16 4 nc = 5 t1 agnd;3,4,5 s6 out1 tp45 wht 12 r9 1.92k tp36 wht refio 1 2 c14 0.1 f dut and analog output signal conditioning 1 2 3 a b jp15 avdd mode acom bl1 bl2 1 2 c16 22nf 12 r15 256 1 2 c17 22nf 12 r14 256 jp10 tp35 wht r12 val 1:1 3 2 16 4 nc = 5 t2 agnd;3,4,5 s11 out2 bl3 bl4 figure 46. AD9763 and output signal conditioning
rev. b AD9763 22 figure 47. assembly, top side
rev. b AD9763 23 figure 48. assembly, bottom side
rev. b AD9763 24 figure 49. layer 1, top side
rev. b AD9763 25 figure 50. layer 2, ground plane
rev. b AD9763 26 figure 51. layer 3, power plane
rev. b AD9763 27 rev. b figure 52. layer 4, bottom side
28 c3582a 0 2/00 (rev. b) printed in u.s.a. AD9763 rev. b outline dimensions dimensions shown in inches and (mm). 48-lead thin plastic quad flatpack (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35)

▲Up To Search▲

Price & Availability of AD9763

	To Download AD9763 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .